The present invention relates generally to PIN driver integrated circuits, and more particularly, to a high speed PIN driver integrated circuit architecture that is suitable for commercial automatic test equipment (ATE) applications to test CMOS, TTL, ECL, low level differential interfaces, such as differential field effect transistor (DFET) GaAs interfaces, and low level CMOS (LVCMOS) interfaces, for example, at very high speeds.
Commercial automatic test equipment systems, such as digital testers, and the like, typically use 500-600 PIN driver circuits per test head, and several test heads per system. Prior art PIN drivers include those developed by such manufacturers as Elantec, Inc., Analog Devices, Inc. and Harris Semiconductor, Inc. for example. The Elantec, Inc. architecture was disclosed at the IEEE 1992 Bipolar Circuits and Technology Meeting. The Analog Devices PIN driver architecture is disclosed in U.S. Pat. No. 5,179,293. The Harris Semiconductor, Inc. architecture was also disclosed in a paper given at the IEEE 1992 Bipolar Circuits and Technology Meeting.
The Elantec, Inc. architecture with a process that can withstand large reverse-bias on the base-emitter junction of the devices. As a result, the achievable performance of this device is in the 25-50 MHz range. The present invention was developed to test SRAM devices operating at greater than or equal to 600 MHz based on the use of a RAMBUS architecture, and therefore the architecture used in the Elantec, Inc. device cannot be implemented in a high speed integrated circuit. This is a direct result of the trade-off between high reverse breakdown and high speed operation for a device.
The Analog Devices PIN driver architecture is disclosed in U.S. Pat. No. 5,179,293. In the Analog Devices driver, as is shown in the figure on the cover page of U.S. Pat. No. 5,179,293, transistors Q40, Q54, Q50 and Q51 rely on clamping action that has been previously described. The clamping approach results in slow response times. Also, the clamping approach of U.S. Pat. No. 5,179,293 suffers from the reverse base-emitter breakdown voltage problem previously described. Resistors have been added to this circuit in an attempt to current-limit the resulting leakage and help with the breakdown problem, but the resistors are very small due to the large switching currents. Also the bias cancellation scheme relies on beta matching to cancel the inhibit mode bias current. The present invention uses a replica bias to obtain improved input current cancellation.
The approach taken by Harris Semiconductor, Inc. is to try to solve the problem with reverse base-emitter breakdown. This can be seen with reference to FIG. 2 of the Harris paper and in particular transistors Qod3a, QC3, Qod3b shown in FIG. 2. What Harris is trying to do is distribute the worst case 9 Volt reverse bias voltage across three base-emitter junctions. The problem is that there is no guarantee that this voltage will distribute evenly, and thus there will be reverse leakage currents that result which poses reliability problems, degrades the forward characteristics of the device and supplies unacceptable PIN leakage currents when the circuit operates in Inhibit mode.
In order to develop a commercial PIN driver integrated circuit, a unique solution must be provided that overcomes the limitations of the prior art. This unique solution also must outperform available prior art drivers in order to allow the product to be a commercial success. As a result, the inherent limitations of prior art PIN driver architectures must be overcome. This includes reverse base-emitter breakdown and input PIN leakage current during Inhibit mode while at the same time allowing for a high speed process to be used to allow for high frequency operation. The present invention provides for such an PIN driver integrated circuit architecture.
It would therefore be desirable to have a high speed PIN driver integrated circuit architecture that overcomes the limitations of prior art approaches. Accordingly, it is an objective of the present invention to provide for an improved high speed PIN driver integrated circuit architecture adapted for commercial automatic test equipment applications. It is another objective of the present invention to provide for an improved high speed PIN driver integrated circuit architecture that may be used to test CMOS, TTL, ECL, low level differential, and LVCMOS interfaces at very high speeds.